1. Technical Field
The present disclosure relates to a method of manufacturing a semiconductor substrate and the semiconductor substrate.
2. Related Art
A higher integration density and a higher functionality are always required of a semiconductor substrate. In the related art, wirings are formed on the semiconductor substrate as finer patterns and the wirings are provided at a higher density. Thus, a higher integration density and a higher functionality of the semiconductor substrate can be achieved. For example, JP-A-2000-59026 discloses a semiconductor substrate in which wiring patterns are formed by forming a plurality of layers on the substrate, and then the wiring patterns are electrically connected to each other by filling a conductor in respective via holes formed through insulating layers.
FIGS. 4A to 6C show a related art manufacturing method of a semiconductor substrate. Firstly, a first wiring pattern 120 is formed on a core substrate 110 (FIG. 4A), and the first wiring pattern 120 is covered with an insulating layer 130 (FIG. 4B). Then, a via hole 160 is formed through the insulating layer 130 such that the first wiring pattern 120 is exposed, by a laser beam machining (FIG. 4C), and a plating seed layer 170 is formed on a surface of the insulating layer 130 and inner surfaces of the via holes 160 by a copper electroless plating (FIG. 4D).
Then, a plating resist 140 is formed on a surface of the plating seed layer 170 (FIG. 5A), then a pattern forming mask 150 is arranged on the plating resist 140 and the plating resist 140 is exposed (FIG. 5B) and developed (FIG. 5C). Thus, grooves 142, 143 are formed through the plating resist 140.
Then, copper plating layers 172 (182) are formed in the grooves 142, 143 by the copper electrolytic plating using the plating seed layer 170 as a power feeding layer (FIG. 6A), and then the plating resist 140 is removed by an etchant (FIG. 6B). Then, portions of the plating seed layer 170 covered with the plating resist 140 are soft-etched using sulfuric acid-hydrogen peroxide etchant, and thus an second wiring pattern 180 and a through via 182 are formed (FIG. 6C).
In the above described method of manufacturing the semiconductor substrate, the first wiring pattern 120 and the second wiring pattern 180 are electrically connected to each other via the through via 182 formed in the via hole 160. Therefore, the via hole 160 and the groove 143 need to be aligned precisely with each other. More concretely, in forming the groove 143, the pattern forming mask 150 need to be arranged on the plating resist 140 to be positioned precisely in the position of the via hole 160.
In arranging the pattern forming mask 150 on the plating resist 140, the pattern forming mask 150 is aligned while using the via hole 160 formed in the insulating layer 130 as an alignment reference position. At this time, on account of an operation precision of the equipment for arranging the pattern forming mask 150 and expansion/contraction of the core substrate 110 in manufacturing step, it is not easy to position the pattern forming mask 150 such that the mask 150 is aligned precisely with all via holes 160 formed in the core substrate 110.
In order to solve such displacement, in the related art, the groove 143 communicated with the via hole 160 is formed to have a larger diameter than the via hole 160 so that displacement between the via hole 160 and the groove 143 is permissible. However, when forming the plating resist 140 through the exposure and development using this pattern forming mask 150, the groove 143 positioned just above the via hole 160 has a diameter larger than the via hole 160, and thus a planar dimension of the through via 182 is increased. Therefore, a pattern forming area of the second wiring pattern 180 is narrowed. As a result, such a problem exists that the design of the second wiring pattern 180 is restricted.